1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including a logic and a memory merged therein, and a function of preventing increase in an abnormal electric current on power-up. Particularly, it relates to prevention of the abnormal electric current in a semiconductor integrated circuit of two external power supply scheme.
2. Description of the Prior Art
In a system LSI in which a DRAM and a logic, such as a processor or an ASIC (application specific IC), are merged, by connecting between the DRAM and the logic by using a multiple-bit, such as 128-bit, . . . , or 512-bit, internal data bus, it is possible to achieve a high data rate transmission speed which is about one or two orders of magnitude faster compared with a case to connect them with each other on a printed board. Furthermore, it is possible to reduce the number of pins of external I/O compared with a system configuration including a general-purpose DRAM located outside, and to decrease the parasitic impedance of the I/O line by one order or more. Therefore, such a system LSI can greatly reduce current, and contribute to enhancing of the performance of information processing equipment that processes a large amount of data, such as 3D graphic processing equipment or image and speech processing equipment.
FIG. 18 is a block diagram showing the structure of a general system LSI including a logic and a DRAM merged therein. In the figure, reference numeral 1 denotes a large-scale logic, and numeral 2 denotes external pins of this large-scale logic 1. Reference numeral 3 denotes an analog core that processes an analog signal, and numeral 4 denotes analog pins of this analog core 3. Reference numeral 5 denotes a DRAM core connected with the large-scale logic 1 via internal interconnections, for storing data which are needed by the large-scale logic 1, numeral 6 denotes a test interface circuit (hereafter abbreviated as TIC) that disconnects the large-scale logic 1 from the DRAM core 5 in test mode, numeral 7-1 denotes test pins that are connected with the DRAM core 5 by the TIC 6 in test mode, and numeral 7-2 denotes a power supply pin via which an external power supply voltage exVDD is supplied to the DRAM core 5.
In operation, the large-scale logic 1 executes an instructed processing based on an instruction input via the external pins 2, and outputs the execution result via the external pins 2. The analog core 3 is connected between the large-scale logic 1 and the analog pins 4, and performs a processing on analog signals. The processing performed by the analog core 3 includes generation of an internal clock signal using a phase-locked loop (PLL), conversion of an analog signal from outside the chip into an equivalent digital signal using an analog-to-digital converter, conversion of a digital signal from the large-scale logic 1 into an equivalent analog signal using a DAC, etc. The TIC 6 disconnects the large-scale logic 1 from the DRAM core 5, and connects the test pins 7-1 with the DRAM core 5 when the chip is placed in test mode. In test mode, a test is carried out on the DRAM core 5 with a tester connected by way of the test pins 7-1 to the chip.
FIG. 14 is a block diagram showing the structure of the DRAM disposed in the prior art semiconductor integrated circuit. In the figure, reference numeral 8 denotes a central control circuit block, numeral 9 denotes a command decoder/control circuit, numeral 10 denotes a row address input buffer/latch/refreshing counter, numeral 11 denotes a row pre-decoder, numeral 12 denotes a column address input buffer/latch, numeral 13 denotes a column pre-decoder, numeral 14 denotes a data I/O controller, numeral 15 denotes an internal power supply voltage generation circuit/self-refresh timer block, numeral 16 denotes a memory array, numeral 17 denotes a sense amplifier band, numeral 18 denotes a row/column local control band, and numeral 19 denotes a data path band.
The central control circuit block 8 latches various external control signals given from outside the block in synchronization with a clock signal CLK, decodes them, and activates two or more internal control signals in response to an internal command specified by the decoded external control signals. The internal power supply voltage generation circuit of the internal power supply voltage generation circuit/self-refresh timer block 15 generates a boosted voltage VPP, a power supply voltage VCCP for peripheral circuits, an array power supply voltage VCCS, a precharge voltage VBL, a cell plate voltage VCP, and a substrate voltage VBB.
FIG. 19 is a block diagram showing the structure of such a prior art internal power supply voltage generation circuit. In the figure, reference numeral 20 denotes a level shifter, numeral 21 denotes a VBB generation circuit, numeral 22 denotes a reference voltage generation circuit, numeral 23 denotes a VCCS generation circuit (hereafter abbreviated as VDCS), numeral 24 denotes a VBL/VCP generation circuit, numeral 25 denotes a VPP generation circuit, and numeral 26 denotes a VCCP generation circuit (hereafter abbreviated as VDCP). Each of the VBB generation circuit 21, the VDCS 23, the VPP generation circuit 25, and the VDCP 26 has an active circuit with a large current-feed ability and a standby circuit with a small current-feed ability in parallel.
In the internal power supply voltage generation circuit, to maintain the voltage levels of the plurality of internal power supplies during the standby period of the DRAM, the standby circuits of the VBB generation circuit 21, the VDCS 23, the VPP generation circuit 25, and the VDCP 26 are always activated.
When the decoded control signals associated with an internal command issued indicate row activation, the active circuits of the VBB generation circuit 21, the VDCS 23, the VPP generation circuit 25, and the VDCP 26 are activated according to an ACTOR signal issued by the command decoder/control circuit 9.
The VDCS 23 is provided with a VCCS abnormality detector for always monitoring the array power supply voltage VCCS, and when the voltage decreases abnormally, raises its output signal from a xe2x80x9cLowxe2x80x9d level to a xe2x80x9cHighxe2x80x9d level. Furthermore, the VDCP 26 is provided with a VCCP abnormality detector for always monitoring the power supply voltage VCCP, and when the voltage decreases abnormally, raises its output signal from a xe2x80x9cLowxe2x80x9d level to a xe2x80x9cHighxe2x80x9d level. Similarly, the VPP generation circuit 25 is provided with a VPP abnormality detector for always monitoring the boosted voltage VPP, and when the voltage decreases abnormally, raises its output signal from a xe2x80x9cLowxe2x80x9d level to a xe2x80x9cHighxe2x80x9d level. As a result, the active circuits of the VDCS 23, the VPP generation circuit 25, and the VDCP 26 are activated respectively. When the voltage of one above-mentioned internal power supply generated decreases abnormally even during the standby period, a corresponding active circuit within the VDCS 23, the VPP generation circuit 25, or the VDCP 26 receives the output signal of a corresponding abnormality detector, and is then activated. Thus, the internal power supply voltage generation circuit can thus recover the abnormally-decreased voltage of an internal power supply to its normal value by activating a corresponding active circuit.
As shown in FIG. 15, the memory array 16 is divided into a number of submemory arrays (SMA) 27. Two subword driver bands (SWD) 28 and two sense amplifier bands (S/A) 29 are arranged around each of the plurality of submemory arrays 27. A plurality of main word lines 30 are arranged in a series of two or more submemory arrays 27 arranged in a row so that they extend in the row and are across the two or more submemory arrays 27. Two or more subword lines 32 are connected with each main word line 30 by way of subword drivers 31. Each main word line 30 is driven by a main word driver (MWD) 34 that operates from a signal from a row decoder (RD) 33.
Furthermore, the row/column local control band 18 consists of a row decoder 33, a column decoder (not shown in the figure), a main word driver 34, and a row local control circuit 35 containing a sense amplifier drive signal generation circuit and a subdecode signal generation circuit. FIGS. 16(a) to 16(c) are diagrams showing the structure of the row/column local control band 18. The column decoder is omitted in this figure.
As shown in FIG. 16(a), the row decoder (RD) 33 includes a circuit for generating a selection signal to select a main word line from a block decode signal BS, pre-decode signals 1 to 3, and a timing control signal RXT, and a circuit for generating a selection signal to select a subdecode line from the block decode signal BS, a pre-decode signal 0, and a timing control signal RXACT. The main word driver 34 includes a circuit for driving a main word line (MWL) having an amplitude at the VPP level in response to the selection signal to select the main word line, which is generated by the row decoder 33.
The row local control circuit 35 includes a circuit for driving a subdecode line (ZSDF) in response to the selection signal to select the subdecode line, which is generated by the row decoder 33, a circuit for generating a ZRST signal to return both the main word line and the subdecode line to the VPP level when the assertion of the decoded control signals is reset, and a circuit for generating a group of sense amplifier control signals, a shared gate signal BLI, a bit line precharge signal BLEQ, and sense activation signals S0N and ZS0N. The level shifter shown in FIG. 16(b) or 16(c) generates the ZRST signal with an amplitude at either the VPP level or the exVDD level, BLI signal, BLEQ signal, and the S0N signal of the above-mentioned sense amplifier control signals from the block decode signal BS at the VCCP level and the control signal RXACT signal.
FIG. 17 shows the connection between each submemory array 27 in FIG. 15 and both a subword driver band 28 and a sense amplifier band 29 arranged around each submemory array 27. Each submemory array 27 includes a plurality of memory cells (not shown in the figure) arranged in the form of an array, and the gates of a plurality of memory cells arranged in the same row is connected with an identical subword line 32. The subword line 32 is connected with each subword driver 31 located in one subword driver band 28 surrounding each submemory array 27. A plurality of memory cells arranged in the same column are connected with either a pair of bit lines BLL and ZBLL or another pair of bit lines BLR and ZBLR. Each of these two bit line pairs is connected with a sense transistor by way of a bit line separation transistor having a gate to which a shared gate signal BLIL or BLIR is input. A pair of bit line equalize/precharge transistors can be arranged on the sense transistor side, i.e., inside the pair of bit line separation transistors in the sense amplifier 36, not outside the pair of bit line separation transistors as shown in FIG. 17.
Each main word line 30 and each subdecode line (ZSDF) 40 are both maintained at the VPP level in the state of non-selection. The levels of a main word line 30 and a subdecode line 40 selected fall from the VPP level to a xe2x80x9cLowxe2x80x9d level when the decoded control signals associated with an internal command issued indicate row activation. In the subword driver 31 arranged in the intersection shown in FIG. 17, a signal SD from the subdecode driver 37 connected with the selected subdecode line 40 changes from the xe2x80x9cLowxe2x80x9d level to the VPP level, and a signal ZSD changes from the VCCS level to the xe2x80x9cLowxe2x80x9d level. The subword driver 31 raises the level of the subword line 32 selected by a main word line 30 and a subdecode line 40 from a xe2x80x9cLowxe2x80x9d level to the VPP level in response to these signal changes. When the assertion of the decoded control signals is reset by an internal precharge command or the like for the DRAM to return to the standby state, the main word line 30 and the subdecode line 40 which have been selected return to the VPP level again, and the level of the subword line 32 falls from the VPP level to the xe2x80x9cLowxe2x80x9d level.
The pair of bit line separation transistors is maintained at the VPP level before the corresponding subword line 32 rises. Furthermore, since the two bit line precharge signals BLEQL and BLEQR are at a xe2x80x9cHighxe2x80x9d level, the pair of bit line equalize/precharge transistors maintains the two bit line pairs at the bit line precharge voltage level VBL, respectively. The gate levels of one of the pair of bit line separation transistors and a corresponding one of the pair of bit line equalize/precharge transistors fall to the xe2x80x9cLowxe2x80x9d level immediately before the subword line 32 rises. Thus, when the pair of bit lines BLL and ZBLL enters a floating state while it is held at the bit line precharge voltage level VBL, and a corresponding subword line 32, rises, the storage node of the selected memory cell is connected with one of the bit line pair, and the electric charge on the capacitor in the memory cell is readout to the bit line pair. By making the sense activation signal S0N become a xe2x80x9cHighxe2x80x9d level and making the ZS0N signal become a xe2x80x9cLowxe2x80x9d level when the electric charge of the memory cell is completely read out to the bit line pair, the sense drive circuit 38 arranged in the intersection of FIG. 17 is made to operate, and all sense transistors on the corresponding sense amplifier band 29 are activated together by the output signals S2P and S2N of the sense drive circuit 38.
General-purpose DRAMs are so structured as to generate all internal power supply voltages VPP, VCCS, VCCP, VBL, VCP, and VBB from one 3.3V external power supply exVDD for example. FIG. 20 schematically shows the rises of main ones of those internal power supply voltages generated when turning on one external power supply exVDD for such a general-purpose DRAM. In the internal power supply voltage generation circuit/self-refresh timer block 15 shown in FIG. 19, a power-on reset signal POR not shown in the figure rises as the external power supply exVDD rises. As a result, each circuit of the internal power supply voltage generation circuit unit starts operating, and the output of each circuit reaches a desired voltage after the expiration of a fixed time interval. As a result, the chip becomes a standby state.
When a DRAM merged with a logic in one chip uses one external power supply, a sequence for turning on a power supply that is the same as that for general-purpose DRAMs is executed and all main word lines (MWL), all subdecode lines (ZSDF), and the BLI signal remain at the VPP level in the row/column local control band 18 shown in FIG. 16. In addition, the BLEQ signal remains at the exVDD level, the S0N signal remains at a xe2x80x9cLowxe2x80x9d level, and the ZS0P signal remains at the VCCP level, so that the DRAM is held in a standby state.
However, in a system LSI with a built-in DRAM shown in FIG. 18, the large-scale logic 1 can operate from a lower logic voltage VLOGIC than the external power supply exVDD supplied to the DRAM core 5 for power consumption decrease. When the power supply voltage VCCP supplied to the DRAM core 5 can be set to be the same as the logic voltage VLOGIC, to decrease the power consumption in the DRAM core 5, instead of using the VDCP 26 in the internal power supply voltage generation circuit/self-refresh timer block 15 of the DRAM core 5, the power supply voltage VCCP can be generated directly from the logic power supply VLOGIC. The DRAM can be of two external power supply scheme. When the power supply voltage VCCP is supplied from outside the DRAM, power consumption can be decreased and a drop in the power supply voltage VCCP under operating conditions can also be prevented.
FIG. 21 is an explanatory drawing schematically showing the rise of each internal power supply voltage when turning on two external power supplies in such a two external power supply scheme. This figure shows the case to turn on the logic voltage VLOGIC (i.e., the power supply voltage VCCP for peripheral circuits) after the expiration of a fixed time interval since the external power supply exVDD of 3.3V was turned on. When those power supplies are turned on in the reverse order, a lot of locations to which the voltage VCCP is connected exist in diffusion nodes within a well in a floating state wherein it has not been biased with VPP, VCCS, and VBB yet. Therefore, there is a danger that latch-up is caused by the electric current flowing into the well, and it is therefore preferable to turn on the power supplies by following the sequence shown in FIG. 21.
However, while the power supply voltage VCCP for peripheral circuits is 0V, the power supply voltages exVDD and VPP rise in the level shifter shown in FIG. 16(b) and 16(c). In this case, according to a large and small relationship of an off leakage current in the two N-channel transistors in the level shifter and the rise speed of the power supply exVDD or VPP, the output of the level shifter becomes either a xe2x80x9cHighxe2x80x9d level or a xe2x80x9cLowxe2x80x9d level, that is, the output of the level shifter becomes an indeterminate state. Therefore, there may be the case the signal ZS0P is at a xe2x80x9cLowxe2x80x9d level when the signal S0N falls into a xe2x80x9cHighxe2x80x9d state, for example, the sense drive circuit 38 shown in FIG. 17 is activated.
In addition, if the signal BLEQ has fallen into a xe2x80x9cHighxe2x80x9d state in the row local control circuit 35 shown in FIG. 16(a), the sense drive circuit 38 is activated while the two bit line pairs and the lines S2P and S2N shown in FIG. 17 are equalized. As a result, a large penetration electric current flows from the voltage VCCS to GND. The voltage VCCS decreases by this penetration electric current, and the VCCS abnormality detector that is the voltage level detector in the VDCS 23 shown in FIG. 19 reacts. Therefore, the active VDCS is activated, and a large current flows from the external power supply exVDD.
On the other hand, the main word line (MWL) and the subdecode line (ZSDF) fall into a middle level without rising to the VPP level since the signal ZRST shown in FIG. 16(a) becomes an indeterminate state, too. As a result, there is a possibility that the penetration electric current keeps flowing in a lot of circuits and elements connected with the power supply VPP. In this case, the voltage VPP decreases and the VPP abnormality detector in the VPP generation circuit 25 shown in FIG. 18 therefore reacts. Therefore, the active VPP generator is activated, and a large current flows from the external power supply exVDD.
For example, Japanese patent application publication (TOKKAIHEI) No. 9-98083 showing a level shifter that is reset by a power-on reset signal and Japanese patent application publication (TOKKAIHEI) No. 7-231252 showing prevention of a penetration electric current by adding a pull-up resistor or a pull-down resistor to a level shifter, etc. disclose such prior art semiconductor integrated circuits as mentioned above.
A problem with a prior art semiconductor integrated circuit constructed as above is that when a DRAM included in the semiconductor integrated circuit is of two external power supply scheme, a penetration electric current flows due to an indeterminate output of a level shifter of a row local control circuit, a voltage VCCS or VPP decreases due to the penetration electric current and therefore either a VCCS abnormality detector of a VDCS or a VPP abnormality detector of a VPP generation circuit reacts, and an active VDCS or an active VPP generator is activated and a large current flowing from an external power supply exVDD causes an abnormal increase in the amount of current flowing in the semiconductor integrated circuit.
The present invention is proposed to solve the above-mentioned problem, and it is therefore an object of the present invention to provide a semiconductor integrated circuit that prevents an abnormal increase in the amount of current flowing in the semiconductor integrated circuit until internal power supply voltages rise at fixed levels on power-up even when a DRAM included in the semiconductor integrated circuit is of two external power supply scheme.
In accordance with an aspect of the present invention, there is provided a semiconductor integrated circuit including a logic, a memory, and a voltage generation unit for generating two or more internal power supply voltages based on two or more external power supply voltages supplied from outside the voltage generation unit with different timings and for furnishing the plurality of internal power supply voltages to the memory, the voltage generation unit comprising: a standby unit with a small current-feed ability that is always activated, for generating the plurality of internal power supply voltages; an active unit with a large current-feed ability that is activated as needed, for generating the plurality of internal power supply voltages; and an activation control unit for preventing the active unit from being activated until all of the plurality of external power supply voltages rise.
In accordance with another aspect of the present invention, the activation control unit is an activation signal control circuit for outputting an activation signal to activate the active unit after all of the plurality of external power supply voltages rise.
In accordance with a further aspect of the present invention, the activation control unit is an activation signal control circuit for outputting an activation signal to activate the active unit in response to a power-on reset signal generated after all of the plurality of external power supply voltages rise.
In accordance with another aspect of the present invention, the activation control unit includes a level shifter provided with either a pull-up transistor or a pull-down transistor, for converting a level of the activation signal to activate the active unit.
In accordance with a further aspect of the present invention, the activation control unit includes a level shifter provided with a substrate bias control circuit for throwing he level shifter out of balance, for converting a level of he activation signal to activate the active unit.
In accordance with another aspect of the present invention, there is provided a semiconductor integrated circuit including a logic, a memory, and a voltage generation unit for generating two or more internal power supply voltages based on two external power supply voltages supplied from outside the voltage generation unit with different timings and for furnishing the plurality of internal power supply voltages to the memory, the circuit comprising: a main power source line to which one of the two external power supply voltages which rises later is applied; a sub-power source line for supplying the external power supply voltage which rises later to a peripheral circuit block; and a precharge unit for disconnecting the sub-power source line from the main power source line until a power-on reset signal is generated in response to a rising of the external power supply voltage which rises later, and for charging the sub-power source line up to a fixed level.
In accordance with a further aspect of the present invention, the precharge unit precharges the sub-power source line up to the fixed level until the power-on reset signal is generated in response to the rising of the external power supply voltage which rises later after another power-on reset signal is generated in response to a rising of the other one of the two external power supply voltages which rises previously.
Further objects and advantages of the present invention will be apparent from the following description of the preferred embodiments of the invention as illustrated in the accompanying drawings.